1. Field of the Invention
The present invention relates to a semiconductor apparatus manufactured using a standardized semiconductor chip, such as a gate array, and more particularly, to a semiconductor apparatus having a circuit combined with a large-size built-in circuit element, for example, a crystal oscillation circuit having a feedback resistance therein.
2. Description of the Related Art
A semiconductor integrated circuit having a microprocessor, analog-to-digital converter, a PLL (Phase-Locked Loop) or the like, generates clock signals by using, for example, a crystal oscillation circuit. The oscillation circuit usually requires a feedback resistance. With improvement in the performance and the size reduction of the semiconductor apparatus, a trend has arisen that the feedback resistor is, together with the oscillation circuit, integrated on one semiconductor chip.
In order to timely provide a variety of semiconductor apparatuses which are capable of meeting particular purposes of users, development of an ASIC (Application-oriented Specific IC) based on a so-called gate array and a standard cell has been performed energetically.
An ASIC of the foregoing type is generally structured as shown in FIG. 1 so that, for example, a basic cell region 6 is formed at the central portion of a semiconductor chip 1, the basic cell region 6 having a multiplicity of transistors (omitted from illustration) disposed in accordance with a predetermined configuration rule. By adequately connecting the foregoing transistors, a desired logical circuit, a memory and other function circuit blocks can be constituted. A plurality of input/output interface circuit (input/output buffer) cells 3 for establishing connections between the foregoing function circuit blocks and circuits outside the chip are disposed around the basic cell region 6. The plurality of the circuit cells 3 are disposed on the edges of the chip 1. The input/output interface circuit cells 3 are hereinafter called I/O cells.
Similar to the basic cell region 6, each I/O cell 3 has a plurality of transistors (omitted from illustration), which are connected by internal circuits, so that an input/output interface circuit having a predetermined function is created.
The various function circuit blocks in the basic cell region 6 and the predetermined I/O cells 3 are connected by signal lines L1. A wiring line (omitted from illustration) is also arranged between each I/O cell 3 and the corresponding bonding pad 2.
A crystal oscillation circuit of the foregoing type is formed in the I/O cell 3. Large circuit elements, such as the feedback resistors, of the oscillation circuit, are usually formed in vacant spaces at the corners of the semiconductor chip 1 to prevent a decrease in the degree of integration. Therefore, the oscillation circuit comprising the feedback resistor must be formed by using an I/O cell 3a most adjacent to the feedback resistor, which is the outermost I/O cell 3a. The reason for this is that a signal line L2, for establishing the connection between the I/O cell 3a and the feedback resistor in the vacant space 4, is formed by the same conductor layer with which the signal line L1, arranged between the basic cell region 6 and the I/O cell 3, is formed.
If an intermediate I/O cell, for example, a cell 3b, of an I/O cell column is used to constitute an oscillation circuit, its layout must be designed so that the line L2 and the line L1 do not intersect. If the foregoing requirement is satisfied, the line L2 inevitably has a long and complicated pattern while being disposed adjacent to the line L1 and the other signal lines as shown in FIG. 2. As a result, inductive coupling among the lines L2, L1 and the other lines cannot be prevented. Therefore, stable oscillation cannot be assured. It is not preferred that the line L2 is formed by using a special conductive layer independently from the line L1 and the other signal lines because the overall cost cannot be reduced.
In the conventional ASIC chip, a specific I/O cell 3a, positioned at the outermost position, has been inevitably selected to serve as a partner which constitutes, for example, the oscillation circuit with the feedback resistance. Therefore, the position of an input/output pin (a pin of a package for accommodating the semiconductor chip), for establishing the connection between the oscillation circuit, and of an external circuit have been inevitably determined.
However, the configuration of the input/output pins of the foregoing ASIC should be easily changeable to allow adaptability to the layout of a circuit pattern on a printed circuit board designed by a user.
Both the cost and the level of difficulty are high because the circuit pattern on the printed circuit board, on which the ASIC is mounted, is complicated and densely mounted due to the current trends of improving performance, reducing size and the increasing variety of equipment using the ASICs. The package pin, corresponding to the outermost cell region selected due to the foregoing reason, is inevitably determined, thereby causing the package pin position to restrict the user in designing a printed circuit pattern. Therefore, completing the design takes an enormous amount of time and reducing the cost is virtually impossible.